There is a continuing trend in the semiconductor industry to fabricate integrated circuits of increasing complexity. In recent years, integrated circuit fabrication technology has achieved the ability to define circuit components having feature sizes in the sub-micron size range. For example, new lithographic techniques have been developed using X-ray and pulse-laser energy sources. Additionally, film deposition technology now exists which can form thin-film layers having a precisely determined chemical composition and thickness. Furthermore, thin-film etching techniques have been developed that are capable of selectively etching one thin-film composition, while not substantially etching other thin-film compositions present on the semiconductor substrate.
Integrated circuits that take advantage of the improved process capability can be fabricated in a substantially reduced amount of substrate area. However, even with the marked advanced in fabrication technology, achievement of the necessary packing density requires further development of component designs. In an effort to reduce substrate surface area requirements, circuit components are increasingly being fabricated in multiple stacked layers of patterned semiconductor material. The need to use advanced fabrication technology is especially important in view of the increased use of stacked semiconductor layers for the fabrication of complex integrated circuits.
A persistent problem in the fabrication of multiple, stacked layers is the creation of rough and uneven surface topography as each individual layer is formed. The lithographic and etching techniques commonly used to produce patterned semiconductor layers can produce features having sharp edges and corners. The sharp edges and corners contribute to severe topographical contrast as successive pattern semiconductor layers are formed upon one another. Severe topographical contrast can cause current leakage in metal-oxide-semiconductor (MOS) transistors as a result of dielectric thinning on the sharp edges. Additionally, the dielectric thinning over sharp edges can increase the capacitive coupling between the successive layers of patterned conductive or semiconductive material.
To overcome many of the problems associated with the fabrication of multi-layered semiconductor devices, planarization techniques are used to flatten the surface topography, and thereby avoid the propagation of severe surface contrast in overlying layers. Although planarization techniques are effective in reducing the propagation of severe surface contrast, leakage current problems continue to exist in MOS transistors fabricated in stacked layers of semiconductor material. Accordingly, further development of component designs utilizing advanced fabrication technology is necessary to provide improved interconnect structures and MOS transistors in multilayered semiconductor devices.